1. Field of the Invention
The present invention relates to an Analog-to-Digital (A/D) converter configured as a semiconductor integrated circuit, and a method for the A/D converter. More particularly, the present invention relates to a parallel oversampling algorithmic A/D converter and a method therefore. For example, the present invention is preferable to an A/D converter and a method therefore with a middle-to-high precision (12 to 16 bits) and a middle-to-high speed (100 k to 10 MHz) which is equipped in an in-vehicle sensor or a control microcomputer.
2. Description of Related Art
Up to now, an algorithmic A/D converter for a middle precision and middle speed has been employed. The algorithmic A/D converter is also called “cyclic ADC type”. Simply stated, an analog input signal is repeatedly subjected to comparison by a comparator and multiply-by-two operation, to thereby generate digital data in the order from MSB. The multiply-by-two operation is generally conducted by signal arithmetic operation by a switched capacitor using an operational amplifier in CMOS, capacitors, and analog switches.
The algorithmic A/D converter is composed of a switched capacitor arithmetic operation circuit having one operational amplifier or two amplifiers, several comparators, and a control logic. Since the algorithmic A/D converter can be realized with a relatively small chip area, the apparatus is advantageous in the costs. The conventional example of the A/D converter of this type is disclosed in, for example, JP-A 124813/2003.
However, the above-mentioned conventional algorithmic A/D converter suffers from the following problems. That is, the processing speed lowers as the precision is heightened. The causes are stated below.
First, a sampling capacitor large in capacitance is required. The average thermal noise power (which dimension is V2) is expressed by the Vn2 in the following.Vn2=k*T/Cs where k is a Boltzmann constant, T is an absolute temperature, and Cs is a capacitor capacitance. This is also called “kT/C noise (kT on C noise or kT over C noise)”. In fact, the noise of the operational amplifier is added to the capacitor noise.
As described above, the average thermal noise power is inversely proportional to the capacitor capacitance. For that reason, in order to increase the S/N ratio while suppressing the noise, the sampling capacitance must be increased. In order to obtain a precision of 14 bits, a relatively large capacitance of about 4 to 8 pF is required although depending on a range of an input voltage or the noise level of the operational amplifier. That the sampling capacitor is large means that the operating speed cannot be ensured unless the driving performance of the operational amplifier is increased in proportion to the capacitor capacitance. For that reason, the sizes of the respective elements that configure the operational amplifier and a bias current must be increased with the results that the chip area becomes large and a current consumption becomes excessive.
Also, the input sampling capacitor repeats charging and discharging operations. For that reason, kickback noise is generated at the time of switching. The magnitude of the kickback noise gets large in proportion to the capacitor capacitance. This fact means that driving impedance at a fore part of the A/D converter is large, and an influence of the kickback noise on the circuit is large, and an error is large. This will be a problem particularly in the high-precision A/D converter. On the other hand, in order to reduce the impedance of a signal source, an additional amplifier must be added, which is disadvantageous in the circuit costs and the power consumption.
Second, there arises a problem on the matching precision in the capacitor capacitance within a semiconductor integrated circuit. In general, the matching precision is about 10 to 12 bits. This is because the capacitance of the respective capacitors within the same chip is slightly uneven due to the manufacturing variation. For that reason, in order to obtain the precision of 14 bits or higher, a capacitance ratio independent algorithm is required. The algorithm of that type is complicated and large in the number of arithmetic operation steps, and long in conversion time. This problem can be eliminated by trimming the capacitor, but the trimming causes an increase in the costs.
Third, a high-gain operational amplifier is required. The gain necessary to obtain a precision of about 14 to 16 bits reaches about 20,000 to 80,000 which are high. Moreover, a wide output range and a high operating speed are required in addition to the high gain. However, an actual problem resides in that it is difficult to design the operational amplifier that is too high in the gain, wide in the output range, and high in the operating speed. This difficulty is especially serious in the case where a supply voltage is low and in the deep sub-micron process.
For example, in the case of a single-stage operational amplifier in a 0.35 μm CMOS process, a supply voltage of 3 V, and a single cascode single gain booster, when transistors are designed with the minimum channel length, the gain is only 10,000 to 20,000, which are short with respect to the required gain. When the channel lengths of the respective transistors are made longer, the gain can be increased. However, this leads to disadvantages such as an increase in the chip area and a degradation in a response speed. Under the circumstances, normally, in the case of obtaining the gain of that level, a circuit configuration with a two-stage operational amplifier is used, or an additional gain booster is equipped. It is needless to say that this structure is disadvantageous in the costs.
On the other hand, as the high-precision A/D converter architecture, there is a sigma-delta (hereinafter referred to as “ΣΔ”) modulation type. The ΣΔ modulator can be structured with several switched capacitor integrators with the operational amplifier. In addition, the ΣΔ modulator has such advantages that the characteristic does not depend on a variation in the capacitor, and the output is either 0 or 1, and basically linear. The ΣΔ modulator is used for a high-precision (enabling 16 bits or more) A/D converter.
However, the ΣΔ modulator requires about several tens to several hundreds as the oversampling ratio, and does not suit the high speed processing. Also, the ΣΔ modulator requires a digital decimation filter at a post stage, which is normally a large-scale logic circuit. Because the fine CMOS cannot be used, for example, in an in-vehicle 5 V power integrated circuit, the chip area of the large-scale logic circuit becomes remarkably large. Even though the processing of the digital decimation filter can be realized by a microcomputer, a load of the microcomputer is significantly large in order to obtain the necessary processing speed, so the realization of such microcomputer is not easy.
Also, there is proposed an A/D converter that samples an input signal plural times by using a single ΣΔ modulator, which is called “extended counting ADC”. In other words, the higher-bit value is determined by a digital counter, and thereafter a lower-bit value is determined by using a successive approximation A/D converter, to thereby obtain a final digital value by summing those values. This is disclosed, for example, in D. Seitzer, G. Pretzl, N. A. Hamdy, “Electronic Analog-to-Digital Converters”, New York, John Wiley & Sons, 1984, chapter 3. There is disclosed the combination of the ΣΔ modulator with the successive approximation A/D converter in Christer Jansson, “A High Resolution, Compact, and Low-Power ADC Suitable for Array Implementation in Standard CMOS,” IEEE Transactions on Circuits and Systems-I, vol. 42, pp. 904-912, November 1995.
The ΣΔ modulator can obtain the precision as high as the number of sampling by conducting sampling by plural times when the gain of the operational amplifier is sufficiently high from the linear characteristic that does not depend on the capacitor variation. Also, because the thermal noise is random, S/N or Signal to Noise ratio is improved by the average filter effect of a plural number of sampling. For that reason, the sizes of the structural elements such as the sampling capacitor and the operational amplifier for driving the sampling capacitor may be small. In addition, since the extended counting ADC does not require a large scale digital decimation filter, it is enough with a small-scale digital circuit. From those advantages, the ΣΔ modulator is suitable for downsizing and middle-to-high precision.
However, in fact, the modulator that is high in the conversion speed and the response input frequency could not be realized. The modulator that has been realized up to now can perform only 1 M Samples/s or less. The reasons are stated below.
First, both of the high precision and the high speed cannot be performed at the same time. The high S/N ratio is required for high precision, and for that reason, it is necessary to reduce the thermal noise which is a main component of the noise. As its countermeasures, there can be mentioned two ways that the oversampling ratio is increased and the sampling capacitor is enlarged.
However, when the oversampling ratio is increased, the conversion speed is lowered. This is because the large number of times of sampling is required. Also, the large number of times of sampling serves as a filter that averages a change in the input signals during sampling. For that reason, the high frequency component of the input signal is attenuated. In order to cope with the high frequency signal, the sampling period of time must be reduced. However, this conflicts with increasing the number of times of sampling. For that reason, both of the high precision and the high speed cannot be performed at the same time.
On the other hand, when the sampling capacitor is enlarged, the driving performance of the operational amplifier for driving the sampling capacitor must be also increased. To achieve this, the sizes of the structural elements must be increased, and the power consumption becomes high. This conflicts with the requirements of the high speed and the small chip area. Also, the kickback noise at the time of turning on/off the capacitor cannot be ignored.
A second reason is that a high-gain operational amplifier is required for the high precision. Notwithstanding, this prevents both of the high speed and the high precision from being performed at the same time. This is because an error in the operational amplifier finite gain of the first-order ΣΔ modulator is in proportion to an output voltage divided by the gain. The error is called “integrator leakage”, and in order to reduce the error, it is necessary to suppress the output amplitude and increase the gain of the operational amplifier. In order to obtain the precision of 14 to 16 bits, the gain of 20,000 to 80,000 or higher is required. However, as described above, it is difficult to design the operational amplifier that is high in the gain and wide in the output range. In particular, in the case where the supply voltage is low and the fine CMOS process is used, the sufficient gain cannot be obtained by provision of only the single-stage operational amplifier and the gain booster. For that reason, it is necessary to provide an additional gain booster or two-stage operational amplifiers. In any case, it is difficult to prevent the chip area or the power consumption from increasing.